Method for Forming Semiconductor Contacts

ABSTRACT

In one embodiment of the invention, contact patterning may be divided into two or more passes which may allow designers to control the gate height critical dimension relatively independent from the contact top critical dimension.

CROSS-REFERENCE TO RELATION APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/821,971, filed on Jun. 26, 2007.

BACKGROUND

A semiconductor device, such as a transistor, may include contacts thatconnect a diffusion region or transistor node (e.g., source or drain) inthe substrate to a metal layer. These contacts may be located adjacentto the transistor gate. Contacts may affect the manufacturing yield anddevice performance of the transistor. Unfortunately, an attempt toincrease manufacturing yield may result in diminished deviceperformance. For example, a contact with a larger bottom criticaldimension (CD), located near the diffusion region in the substrate, mayprovide higher performance. However, a smaller CD in the contact nearthe top of the gate, at the gate height, might result in fewer contactto gate (CTG) shorts. Fewer such shorts may result in a bettermanufacturing yield. Thus, increasing the size of a contact may increasedevice performance but at the expense of manufacturing yield.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, incorporated in and constituting a part ofthis specification, illustrate one or more implementations consistentwith the principles of the invention and, together with the descriptionof the invention, explain such implementations. The drawings are notnecessarily to scale, the emphasis instead being placed uponillustrating the principles of the invention. In the drawings:

FIG. 1 is side cross section of a semiconductor device.

FIG. 2 is a side cross section of a semiconductor device in oneembodiment of the invention.

FIG. 3 is a top view of a semiconductor device in one embodiment of theinvention.

FIG. 4 is a method for forming a contact in a semiconductor device inone embodiment of the invention.

DETAILED DESCRIPTION

The following description refers to the accompanying drawings. Among thevarious drawings the same reference numbers may be used to identify thesame or similar elements. While the following description provides athorough understanding of the various aspects of the claimed inventionby setting forth specific details such as particular structures,architectures, interfaces, and techniques, such details are provided forpurposes of explanation and should not be viewed as limiting. Moreover,those of skill in the art will, in light of the present disclosure,appreciate that various aspects of the invention claimed may bepracticed in other examples or implementations that depart from thesespecific details. At certain junctures in the following disclosuredescriptions of well known devices, circuits, and methods have beenomitted to avoid clouding the description of the present invention withunnecessary detail.

FIG. 1 is side cross section of a semiconductor device. Semiconductordevice 100 includes a gate 115, spacers 120, diffusion areas 125, 130,substrate 135, dielectric layer 110, metallization layer 105, andcontact 155.

CTG shorts are dominated by the CD at gate height 145. Thus, a smallerCD at gate height 145 may possibly increase manufacturing yield.However, performance may be proportional to the CD at the bottom of thecontact 150. Specifically, a larger CD at the contact bottom 150 mayincrease device performance. In addition, a larger contact bottom CD 150may promote proper overlap with trenches that may underlie the contact155.

Using traditional techniques, contact 155 is formed using a contactpatterning scheme that includes a single lithography step and a singleetch step. In this “one pass” scheme, the contact etch carries along aconsistent taper along the bottom sidewall 160 and top sidewall 165 ofthe contact 155.

FIG. 2 is a side cross section of a semiconductor device in oneembodiment of the invention. Semiconductor device 200 includes a gate215, spacers 220, diffusion areas 225, 230 (e.g., source, drain),substrate 235, dielectric layer 210, metallization layer 205, andcontact 255. In one embodiment of the invention, contact 255 has avertical, lower portion 275 and a broader, tapered, upper portion 270.The horizontal cross section of the contact may vary and includes, forexample, circular and trench cross sections.

In contrast to the traditional device of FIG. 1, contact 255 in FIG. 2may be formed using a “dual pass” technique instead of a “single pass”technique. Specifically, the contact patterning may be divided into twoor more passes. In one embodiment of the invention there are twolithography steps and two etching steps. This may allow designers tocontrol the CD at gate height 245 relatively independent from the CD atthe top of the contact 240.

In one embodiment of the invention, the first lithography pass may printthe contact 255 at a first CD 250. In embodiments of the inventionwherein the sidewall 260 of the lower contact is vertical, the CDs atthe contact bottom 250 and gate height 245 are the same. The first etchmay extend from the contact top near the metallization layer 205 all theway to the contact bottom near the substrate 235. A second, subsequentlithography pass would broaden the contact and allow the upper side wall265 to taper and produce a larger contact top CD 240. In one embodimentof the invention, the second etch may extend from the contact top downto the gate height and stop. Stopping the etch at gate height may beaccomplished by timing the etch or with use of a strategically placedetch stop material. Thus, a wider upper contact portion 270 may promotedevice performance while a more narrowed or narrowing lower contactportion 275 may simultaneously promote manufacturing yield by avoidanceof CTG shorts. This scheme maximizes the bottom CD for a given gateheight CD without compromising the metal fill capabilities (as may bethe case with vertical contacts).

FIG. 3 is a top view of a semiconductor device in one embodiment of theinvention. Device 300 includes a metallization layer 305, upper contactportion 370 and a more narrowed lower contact portion 375. However, inthis embodiment of the invention the central vertical axis 372 of thelower contact portion 375 is off-center and non-collinear with thecentral vertical axis 371 of the upper contact portion 370. Thus,splitting contact patterning into bottom contacts and top contactsformed with multiple photolithography passes may allow relative movementof the bottom CD 250 with respect to the CD at the contact top 240. Thismay de-convolute design restrictions on contact to trench overlap andcontact to metal one layer overlap.

FIG. 4 is a method for forming a contact in a semiconductor device inone embodiment of the invention. In block 405, a MOS transistor isprovided. The transistor may include a semiconductor substrate 235. Thesubstrate may be formed using a bulk silicon or a silicon-on-insulatorsubstructure. In other implementations, the substrate may be formedusing alternate materials, which may or may not be combined withsilicon, that include but are not limited to germanium, indiumantimonide, lead telluride, indium arsenide, indium phosphide, galliumarsenide, or gallium antimonide. Although a few examples of materialsfrom which the substrate may be formed are described here, any materialthat may serve as a foundation upon which a semiconductor device may bebuilt falls within the spirit and scope of the present invention.

Each transistor may include a gate stack consisting of a gate electrodeand a gate oxide layer. The gate electrode is a conductive layer thatmay be formed from one or more metal layers. Metal layers that may beused in the gate electrode include, but are not limited to, copper,aluminum, hafnium, zirconium, titanium, tantalum, titanium carbide,zirconium carbide, tantalum carbide, hafnium carbide, aluminum carbide,other metal carbides, ruthenium, palladium, platinum, cobalt, nickel,ruthenium oxide, other conductive metal oxides, titanium nitride,tungsten, tantalum nitride, cobalt, or an alloy of two or more of thesemetals. When the gate electrode is a metal, the corresponding gate oxidelayer may consist of a thin, high-k dielectric layer. High-k dielectricmaterials that may be used for the gate oxide layer include, but are notlimited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide,lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide,tantalum oxide, titanium oxide, barium strontium titanium oxide, bariumtitanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide,lead scandium tantalum oxide, and lead zinc niobate. In alternateimplementations, the gate electrode may consist of a polysilicon layerand its corresponding gate oxide layer may consist of a silicon dioxidelayer.

The gate stack of each MOS transistor may be flanked by at least twodiffusion regions 225, 230. The diffusion regions may form source anddrain regions for each MOS transistor 200. The diffusion regions 225,230 are formed by implanting dopants into regions of the semiconductorsubstrate 235 that are adjacent to the gate stacks 215. These dopantsmay include, but are not limited to, boron, aluminum, phosphorous,arsenic, and antimony.

In block 410, a dielectric layer 210 may be formed atop the MOStransistors. The dielectric layer 210 may be formed from materials suchas silicon dioxide or carbon doped oxide. In some implementations, thedielectric layer 210 may be formed from materials such as siliconnitride, organic polymers such as perfluorocyclobutane andpolytetrafluoroethylene, organosilicate glass, fluorosilicate glass(FSG), organosilicates such as silsesquioxane, and siloxane.

In block 415, a first photolithography process may be carried out toform openings that are in contact with the diffusion regions. Forexample, the first process forms what will be known as the lower contactportion 275. The opening formed by the first process is shown by theside walls 260 and 274 (phantom lines). The side wall 274 will later beremoved and broadened during a second process described below. In oneembodiment of the invention, the side walls 260, 274 are substantiallyvertical. A vertical etch is possible using techniques (e.g., oxygen)known to those of ordinary skill in the art. Vertical profiles can beachieved by minimizing the sidewall polymer deposition during the etchprocess. Typical dielectric etches are carried using high power plasmaand CxFy (e.g., C₄F₆ and C₄F₈) based chemistries. One method to reducesidewall deposition is to increase the oxygen (O₂) content in theplasma. Again, as mentioned above, the openings may have any number ofhorizontal cross-sectional shape (e.g., circular, trench).

The first photolithography process may include depositing a photoresistmaterial on the dielectric layer 210 and patterning the photoresistusing known photolithography techniques to define the diffusionopenings. For example, a photoresist material may be deposited using aspin-on deposition (SOD) process, exposed to radiation (e.g., optical,electron beam, or extreme ultraviolet) through a mask that transfers apattern for the trench openings, and exposed to a developer solution.The photoresist material remaining after development masks selectedportions of the dielectric layer 210 such that any exposed portions willdefine the openings.

The first patterning process may include etching the exposed dielectricmaterial to form diffusion openings. The etching process may be carriedout using an etch chemistry that is appropriate for the dielectricmaterial used. For instance, if the dielectric layer is silicon dioxideor carbon doped oxide, a CxFyHz etch chemistry may be used. For example,a high power plasma etch and CxFy (e.g., C₄F₅ and C₄F₃) based chemistrymay be used. The openings that are formed may be cleaned usingconventional processes, for instance, a plasma clean, a wet chemicalclean, or a combination of both. The openings are in contact with thediffusion regions 225, 230.

In block 420, a sacrificial layer is deposited into the diffusionopenings and onto the dielectric layer 210. The sacrificial layer may beplanarized if needed, for instance, using a chemical mechanicalpolishing (CMP) process. The sacrificial layer may be formed frommaterials that include, but are not limited to, spin-on glass, othersiloxane-based materials, and organic antireflective coatings.Deposition processes such as SOD, chemical vapor deposition (CVD),physical vapor deposition (PVD), or atomic layer deposition (ALD) may beused to deposit the sacrificial layer. The sacrificial layer provides aplanar surface upon which a subsequent photolithography process may becarried out. In addition, the sacrificial layer may be tailored toprovide reflectivity control to enable good patterning quality at thesubsequent photolithography process.

In block 425, a second photolithography process may now be carried outto form the upper contact portion 270. In other words, the secondprocess may remove wall 274 and broaden the upper contact 270 to includetapered walls 265. Of course, the newly formed wall 265 need notnecessarily be tapered. The newly formed contact 255 may later be filledwith metal to form electrical contacts to the diffusion area or anyother area (e.g., gate stack) in need of a contact. For example, inaccordance with implementations of the invention, openings for one ormore local interconnects may also be formed at this process stage.

The second patterning process may be carried out in a similar manner asdescribed above. In accordance with implementations of the invention,the etch chemistry and etch parameters are optimized to ensure that thesacrificial layer and the dielectric layer 210 are etched atsubstantially the same rate. The sacrificial layer, as well as anyremaining photoresist material, may then be removed to expose all of theopenings that have been formed. Methods of removing sacrificial layersand photoresist material are well known in the art, and may include wetchemical etching processes and plasma etching processes.

In block 430, a metallization process may be carried out to fill theopening with a suitable metal to form electrical contacts to thediffusion regions. Metallization processes such as CVD, plasma enhancedchemical vapor deposition (PECVD), PVD, sputter deposition, ALD,electroplating, electroless plating, or a combination of any of theseprocesses, may be used to deposit one or more layers of metal in thetrench openings.

Metals that may be used for the metallization include, but are notlimited to, copper, ruthenium, palladium, platinum, cobalt, nickel,ruthenium oxide, tungsten, aluminum, titanium, tantalum, titaniumnitride, tantalum nitride, hafnium, zirconium, a metal carbide, aconductive metal oxide, or combinations of the above.

The metal layer 205 may consist of multiple layers of metals. Forinstance, in one implementation, a first metal layer may consist of aseed layer, such as a copper seed layer or a noble metal catalyst layer,and a second metal layer may consist of a bulk metal layer such ascopper. In further implementations, the various metal layers may providevarious functionality, such as barrier layers, adhesion layers, andcapping layers. Finally, a CMP process may be utilized, if needed, toplanarize the deposited metal layer. Later, the metal layer may bepatterned to provide proper power connections to various contacts builtusing the methodologies described herein.

While the present invention has been described with respect to a limitednumber of embodiments, those skilled in the art will appreciate numerousmodifications and variations therefrom. It is intended that the appendedclaims cover all such modifications and variations as fall within thetrue spirit, and scope of this present invention.

1. An apparatus comprising: a gate electrode including a top and abottom, said top at a vertical level; and a via that has an inclinedslope that tapers down to the vertical level of the top of the gateelectrode.
 2. The apparatus of claim 1 wherein the via has verticalsides below the top of the gate electrode.
 3. The apparatus of claim 1including a dielectric layer, said gate electrode within said layer. 4.The apparatus of claim 3, said via having a top surface aligned with thetop surface of said layer.
 5. The apparatus of claim 1 wherein said viatapers from said top surface to a narrower cross section at the top ofthe gate electrode.
 6. The apparatus of claim 1 including a source anddrain adjacent said gate.
 7. The apparatus of claim 6, said via makingelectrical contact to said source and drain through a lower portion ofsaid via.
 8. A method comprising: forming a gate electrode over asubstrate, said gate electrode having top and bottom surfaces; forming asource and drain adjacent said gate electrode; and forming a via thatextends from one of said source and drain electrodes upwardly to theupper surface of said gate electrode and then continues upwardly,tapering outwardly.
 9. The method of claim 8 including forming said viawith vertical sides below the top surface of said gate electrode. 10.The method of claim 8 including forming a dielectric having an uppersurface aligned with an upper surface of said via, said gate electrodebeing covered by said dielectric.
 11. The method of claim 10 includingaligning a top surface of the via with the upper surface of said layer.